1. FIELD OF THE INVENTION
This invention relates to semiconductor memories and, more specifically, to nonvolatile capacitor random access memories (NVCRAM).
2. BRIEF DESCRIPTION OF THE PRIOR ART
Most of the nonvolatile memory arrays which are presently available have serious limitations which have limited the market for devices of this type. In general, the nonvolatile RAMs are based upon the six transistor static RAM cell of the type disclosed by S. Saito et. al. in "N-channel High Speed Nonvolatile Static RAM Utilizing MNOS Capacitors", Japanese Journal of Applied Physics, Vol. 19, pages 225-229 (1979) and other publications. Such devices are also based upon a four transistor CMOS NVRAM cell as described in Serial No. 344,339, filed Feb. 1, 1982. Because of the large number of transistors used in these cells, such memory cells are large in size thereby limiting the number of cells that can be formed onto a silicon chip of predetermined area. The many transistors used in the above described prior art nonvolatile static RAM cells are necessary to fully isolate the nonvolatile memory element from various crosstalk mechanisms which are particularly large when the memory element can be programmed and erased at relatively low voltages.
Another approach to nonvolatile memories has been the use of two transistor cells with one memory transistor and one isolation or select transistor as demonstrated by T. Hagiwara et. al., "A 16 kb Electrically Erasable Programmable ROM", Proceedings 1979 ISSCC, pages 51-52 and 227 (1979) and other references. For best operation, these types of cells require four control lines to operate each cell. Since cells of this type are not as well isolated from the programming crosstalk and read disturb mechanisms such cells typically use nonvolitale media which require extremely high voltage, such as 20 to 25 volts and long programming times such-as about 10 milliseconds.
There has been one attempt to use a dynamic RAM-like cell in a nonvolatile memory, but in this attempt, the cells have to be block erased and could not be programmed and erased bit by bit or byte by byte without changing the programming state of unaddressed cells. This dynamic RAN is disclosed by R. Kondo et. al., "Dynamic Injection MNOS Memory Device", Japanese Journal of Applied Physics, Vol. 19, pages 231-237 (1979).
There has also been an attempt to construct nonvolitale RAM cells using two control lines, a nonvolatile insulator and a vertically oriented JFET in a crosspoint capacitor arrangement where the JFET gives additional isolation against crosstalk. This memory has been termed a NVJRAM and is set forth in U.S. Pat. Nos. 4,459 684 and 4,435,785. These cells are small in area, however the protection against crosstalk therein is insufficient for fast programming of nonvolitale media and the capacitance of the bit line used For signal output is slightly sensitive to the state of the programmed cells along the bit line.
The isolation against crosstalk in the NVJRAM has been improved by adding one or two MOSFETs to separate the nonvolatile element From the control lines as demonstrated in Ser. No. 311,101, filed Oct. 13, 1981 of R. Chapman, now abandoned. This memory has improved performance over the NVJRAM, however, unfortunately, it is still large in size with respect to a dynamic RAM cell and uses fabrication procedures which are not compatible with the fabrication of MOSFET peripheral circuits. The vertical JFET in the MOSFET protected NVJRAM is difficult to fabricate and the width of the JFET channel is difficult to reproduce. The efficiency of the program operation to produce the negative threshold state is lowered because of loss of current through the JFET channel by means of a short channel leakage.
In addition to the usual nonvolatile modes of operation, the nonvolatile RAMs based on the six transistors static RAM cell have the attribute of having both volatile and nonvolatile data stored on the chip with the ability to shift data from one form back to the other. This is an advantageous mode of operation but the cell is too large for use in arrays with many elements because the cell contains too many transistors. It is therefore readily apparent that what is needed is a small cell with only a few transistors which can contain both volatile and nonvolatile data. To simplify the operation of this compact cell, the volatile and nonvolatile data should be readable using the same read mechanism.